Process for producing semiconductor integrated circuit device

ABSTRACT

In order to improve the dielectric constant, residual dielectric polarization, hysteresis characteristics, etc. of a high-dielectric or ferroelectric thin film for use in the formation of capacitive insulating films of capacitors of a DRAM or a ferroelectric RAM, a target having a density of at least 90% of the theoretical value is used in forming, by sputtering, a high-dielectric or ferroelectric thin film for use in the formation of capacitive insulating films of capacitors of a DRAM or a ferroelectric RAM.

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application is a Continuation of application Ser. No.09/906,102, filed Aug. 5, 1997, the contents of which are incorporatedherein by reference.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to a process for producing asemiconductor integrated circuit device, and particularly to atechnology effectively applicable to the production of a semiconductormemory device wherein the capacitive insulating films of capacitors areformed of a high-dielectric material or a ferroelectric material.

[0003] A DRAM (dynamic random access memory) has become the mainstreamof large-capacity semiconductor memory devices since it is so simple inmemory cell structure as to be easily miniaturized. It is underinvestigation to use a high-dielectric material of at least 20 inrelative dielectric constant, such as Ta₂O₅ or BST [(Ba,Sr)TiO₃], or aferroelectric material in excess of 100 in relative dielectric constant,such as PZT (PbZr_(x)Ti_(l-x)O₃), PLT (PbLa_(x)Ti_(l-x)O₃), PLZT,PbTiO₃, SrTiO₃, or BaTiO₃ in constituting a DRAM as a countermeasure formaking up for a recent decrease in the amount of electric chargestorable in a capacitor in keeping with the miniaturization of a memorycell.

[0004] On the other hand, in the field of nonvolatile memories, thedevelopment of a ferroelectric RAM wherein the polarization inversion ofthe ferroelectric material mentioned above is utilized for holdingmemories is in progress. The ferroelectric RAM is expected to beutilizable as a substitute for a flash memory or EEPROM since it permitsfrequent data rewriting and has a high rewriting speed. Moreover, theferroelectric RAM is also expected to be utilizable as a substitute foran SRAM for the backup of a battery used in a memory card or the likesince it is reduced in electric current consumption and so simple inmemory cell structure as to permit high-level integration.

[0005] One method of forming a thin film of a high-dielectric orferroelectric material is a sputtering method wherein an inert gas suchas Ar (argon) is impinged against a target made of a hot-pressed sinterof a film-forming material to release clusters of the film-formingmaterial, which are then deposited on a substrate disposed facing thetarget. In a sputtering method wherein use is made of a targetconstituted of a high-dielectric or ferroelectric material, particularlya double oxide having a perovskite crystal structure, examples of whichinclude PZT, PLT, and PLZT, however, it is known that the formation of athin film having a stable composition is difficult for various reasons.

[0006] For example, in Japanese Patent Laid-Open No. 249,278/1990, it ispointed out that a thin film of a ferroelectric material having aperovskite crystal structure such as PZT, when formed by sputtering, isliable to the shortage of oxygen in the thin film. A countermeasure tothis as disclosed in the above patent gazette is a method wherein a thinfilm of a ferroelectric material is formed over a substrate bysputtering and then annealed in high-pressure oxygen to effect oxygenuptake into the film to thereby obtain a dense thin film close to thestoichiometric composition and improved in the degree of orientation.

[0007] In Japanese Patent Laid-Open No. 272,033/1994 directed to aprocess for producing a PZT or PLZT target, it is pointed out that anattempt to make the crystal structure of a target homogeneous and finefor the purpose of decreasing the amount of the formed particlescausative of short circuit and disconnection of wirings in an LSIcomplicates the step of hot-pressing a starting material powder to formthe target, whereby there arise the problems of contamination of oxygen,etc. with impurities and a lot-to-lot variation of oxygen concentration.A countermeasure to this as disclosed in the above patent gazette is thetechnique of forming a target using a starting material powder of acomparatively large particle size obtained by mechanical alloying.

[0008] The above patent gazette also discloses a method wherein theoxygen content of a target is decreased to a value lower than that ofthe stoichiometric composition to control the oxygen content of the filmcomposition. A target produced by this method is formed into a film bysputtering in an inert gas atmosphere or an oxygen atmosphere, followedby annealing at a temperature of 400 to 700° C. if necessary.

[0009] Japanese Patent Laid-Open No. 18,427/1995 and Japanese PatentLaid-Open No. 18,428/1995 both directed to an improvement in asputtering Pb-containing perovskite crystal target such as PZT, PLT orPLZT disclose the technique of decreasing the localized variation of thePb content in a thin ferroelectric film, wherein a Pb-containing doubleoxide and extra PbO which accounts for 5 to 40 wt. % of the whole bodyare hot-pressed and sintered to produce a target, provided that theextra PbO is mainly constituted of PbO having a tetragonal or rhombiccrystal structure.

[0010] In “KYOYUDENTAI HAKUMAKU MEMORY (THIN FERROELECTRIC FILM MEMORY”pp. 187-193, published by Kabushiki Kaisha Science Forum on Jun. 30,1995, it is pointed out that the formation of a thin PZT-sputtered filminvolves re-evaporation of Pb due to the temperature or resputtering topresent the problem of failure in obtaining a thin film having astoichiometric composition. A countermeasure to this as introduced bythe above-mentioned document is multi-component sputtering equipmentwherein a PZT target and a PbO target are simultaneously sputtered tocompensate for re-evaporated Pb by PbO, and a method wherein a thin filmhaving a pyrochlore structure is formed by keeping the temperature of asubstrate low during sputtering and then annealed to convert thatstructure into a perovskite structure.

BRIEF SUMMARY OF THE INVENTION

[0011] Although various methods of attaining an improvement have beenproposed because a thin film having a stable composition can hardly beobtained by sputtering using a target made of a high-dielectric orferroelectric material, particularly a double oxide having a perovskitecrystal structure, the fact is that a sputtering method capable ofproviding a high-dielectric or ferroelectric thin film endowed withdesired properties (e.g., dielectric constant, residual dielectricpolarization, hysteresis characteristics, etc.) has not been developedyet.

[0012] An object of the present invention is to provide a technologyaccording to which a high-dielectric or ferroelectric thin film improvedin dielectric constant, residual dielectric polarization, hysteresischaracteristics, etc. can be obtained.

[0013] The foregoing and other objects and novel features of the presentinvention will become apparent from the description of the specificationtaken in connection with the accompanying drawings.

[0014] The following brief description will be made of the outlines ofrepresentative embodiments of the invention disclosed in the instantapplication.

[0015] (1) The process for producing a semiconductor integrated circuitdevice according to the present invention comprises the use of a targethaving a density of at least 90% of the theoretical value in forming ahigh-dielectric thin film or a ferroelectric thin film over a substrateby sputtering.

[0016] (2) The process for producing a semiconductor integrated circuitdevice according to the present invention comprises:

[0017] (a) installing a target made of a high-dielectric material or aferroelectric material and having a density of at least 90% of thetheoretical value in a target retainer portion provided in the treatmentchamber of sputtering equipment, and disposing a substrate in such a waythat it faces the target;

[0018] (b) applying an RF bias to the substrate while introducing aninert gas into the treatment chamber reduced in pressure to apredetermined degree of vacuum; and

[0019] (c) forming a plasma between the target and the substrate andimpinging ions of the inert gas formed by the discharge of the plasmaagainst the target to deposit clusters of the high-dielectric materialor the ferroelectric material released from the surface of the targetover the substrate to thereby form a high-dielectric thin film or aferroelectric thin film over the substrate.

[0020] (3) The process for producing a semiconductor integrated circuitdevice according to the present invention comprises:

[0021] (a) depositing a first conducting film over a principal plane ofa wafer for use in the production of a semiconductor integrated circuitdevice;

[0022] (b) depositing a high-dielectric thin film or a ferroelectricthin film over the wafer having the first conducting film depositedthereover by sputtering using a target having a density of at least 90%of the theoretical value;

[0023] (c) depositing a second conducting film over the wafer having thehigh-dielectric thin film or the ferroelectric thin film depositedthereover; and

[0024] (d) sequentially etching the second conducting film, thehigh-dielectric thin film or the ferroelectric thin film, and the firstconducting film by using a photoresist as a mask to form capacitors.

[0025] Some other embodiments of the present invention involved in theinstant application will be exemplified in the following itemized form:

[0026] 1. The process for producing a semiconductor integrated circuitdevice, wherein a target having a density of at least 90% of thetheoretical value is used in forming a high-dielectric thin film or aferroelectric thin film over a substrate by sputtering.

[0027] 2. The process for producing a semiconductor integrated circuitdevice as set forth in the above item 1, wherein the relative dielectricconstant of the high-dielectric thin film is at least 20.

[0028] 3. The process for producing a semiconductor integrated circuitdevice as set forth in the above item 1, wherein the relative dielectricconstant of the ferroelectric thin film is at least 100.

[0029] 4. The process for producing a semiconductor integrated circuitdevice as set forth in the above item 1, wherein the ferroelectric thinfilm substantially has a perovskite crystal structure.

[0030] 5. The process for producing a semiconductor integrated circuitdevice as set forth in the above item 1, wherein the ferroelectric thinfilm is electrically capable of polarization inversion.

[0031] 6. The process for producing a semiconductor integrated circuitdevice, comprising:

[0032] (a) installing a target made of a high-dielectric material or aferroelectric material and having a density of at least 90% of thetheoretical value in a target holding means provided in the treatmentchamber of sputtering equipment, and disposing a substrate in such a waythat it faces the target;

[0033] (b) applying an RF bias to the substrate while introducing aninert gas into the treatment chamber reduced in pressure to apredetermined degree of vacuum; and

[0034] (c) forming a plasma between the target and the substrate andimpinging ions of the inert gas formed by the discharge of the plasmaagainst the target to deposit clusters of the high-dielectric materialor the ferroelectric material released from the surface of the targetover the substrate to thereby form a high-dielectric thin film or aferroelectric thin film over the substrate.

[0035] 7. The process for producing a semiconductor integrated circuitdevice as set forth in the above item 6, wherein the ferroelectric thinfilm substantially has a perovskite crystal structure.

[0036] 8. The process for producing a semiconductor integrated circuitdevice, comprising:

[0037] (a) depositing a first conducting film over a principal plane ofa wafer for use in the production of a semiconductor integrated circuitdevice;

[0038] (b) depositing a high-dielectric thin film or a ferroelectricthin film over the wafer having the first conducting film depositedthereover by sputtering using a target having a density of at least 90%of the theoretical value;

[0039] (c) depositing a second conducting film over the wafer having thehigh-dielectric thin film or the ferroelectric thin film depositedthereover; and

[0040] (d) sequentially etching the second conducting film, thehigh-dielectric thin film or the ferroelectric thin film, and the firstconducting film by using a photoresist as a mask to form capacitors.

[0041] 9. The process for producing a semiconductor integrated circuitdevice as set forth in the above item 8, wherein the capacitors are eacha capacitor of a memory cell of a DRAM.

[0042] 10. The process for producing a semiconductor integrated circuitdevice as set forth in the above item 8, wherein the capacitors are eacha capacitor of a memory cell of a ferroelectric RAM.

[0043] 11. The process for producing a semiconductor integrated circuitdevice as set forth in the above item 10, wherein the memory cell of theferroelectric RAM comprises one MISFET and one of the capacitors.

[0044] 12. The process for producing a semiconductor integrated circuitdevice as set forth in the above item 8, wherein the first and secondconducting films are made of one or more metals and/or metal oxidesselected from the group consisting of Pt, Ir, IrO₂, Rh, RhO₂, Os, OsO₂,Ru, RuO₂, Re, ReO₃, Pd, and Au.

[0045] 13. The process for producing a semiconductor integrated circuitdevice as set forth in the above item 8, wherein the ferroelectric thinfilm is made of a ferroelectric material having a perovskite crystalstructure and selected from the group consisting of PZT, PLT, PLZT, SBT,PbTiO₃, SrTiO₃, and BaTiO₃.

[0046] 14. The process for producing a semiconductor integrated circuitdevice as set forth in the above item 8, wherein the high-dielectricthin film or the ferroelectric thin film is annealed in an oxygenatmosphere after the deposition thereof.

[0047] 15. The process for producing a semiconductor integrated circuitdevice, comprising:

[0048] (a) preparing a wafer for use in the production of asemiconductor integrated circuit device, wherein a part or the whole ofeach of a plurality of semiconductor elements is formed on the firstprincipal plane side of the wafer; and

[0049] (b) forming a high-dielectric thin film or a ferroelectric thinfilm, which is to constitute dielectric films for information storage ina volatile or nonvolatile memory, over the first principal plane of thewafer either directly or with a plurality of intermediate filmstherebetween by sputtering using a target having a density of as high asat least 90% of the theoretical density at least in the portion thereofsubject to sputtering.

[0050] 16. The process for producing a semiconductor integrated circuitdevice as set forth in the above item 15, wherein the dielectric filmfor information storage has a relative dielectric constant of at least20 in the final product.

[0051] 17. The process for producing a semiconductor integrated circuitdevice as set forth in the above item 16, wherein the dielectric filmfor information storage substantially has a perovskite structure.

[0052] 18. The process for producing a semiconductor integrated circuitdevice, comprising:

[0053] (a) preparing a wafer for use in the production of asemiconductor integrated circuit device, wherein a part or the whole ofeach of a plurality of semiconductor elements is formed on the firstprincipal plane side of the wafer;

[0054] (b) forming a conducting film, which constitutes a lowerelectrode of a capacitive element for information storage in a volatileor nonvolatile memory, over the first principal plane of the wafereither directly or with a plurality of intermediate films therebetween;

[0055] (c) forming a high-dielectric or ferroelectric thin film, whichconstitutes a film of a capacitive element for information storage in avolatile or nonvolatile memory, over the first principal plane of thewafer having the lower electrode formed thereover either directly orwith a plurality of intermediate films therebetween by sputtering usinga target having a density of as high as at least 90% of the theoreticaldensity at least in the portion thereof subject to sputtering; and

[0056] (d) forming a conducting film, which constitutes an upperelectrode of a capacitive element for information storage in a volatileor nonvolatile memory, over the first principal plane of the waferhaving the dielectric film formed thereover either directly or with aplurality of intermediate films therebetween.

[0057] 19. The process for producing a semiconductor integrated circuitdevice as set forth in the above item 18, wherein the dielectric filmfor information storage has a relative dielectric constant of at least20 in the final product.

[0058] 20. The process for producing a semiconductor integrated circuitdevice as set forth in the above item 19, wherein the dielectric filmfor information storage substantially has a perovskite structure.

[0059] 21. The process for producing a semiconductor integrated circuitdevice, comprising:

[0060] (a) preparing a wafer for use in the production of asemiconductor integrated circuit device, wherein a part or the whole ofeach of a plurality of semiconductor elements is formed on the firstprincipal plane side of the wafer;

[0061] (b) leveling the first principal plane of the wafer having theplurality of semiconductor elements formed thereover by chemicalmechanical polishing; and

[0062] (c) forming a high-dielectric or ferroelectric film, whichconstitutes a dielectric film for information storage in a volatile ornonvolatile memory, over the leveled first principal plane of the wafereither directly or with a plurality of intermediate films therebetweenby sputtering using a target having a density of as high as at least 90%of the theoretical density at least in the portion thereof subject tosputtering.

[0063] 22. The process for producing a semiconductor integrated circuitdevice as set forth in the above item 21, wherein the dielectric filmfor information storage has a relative dielectric constant of at least20 in the final product.

[0064] 23. The process for producing a semiconductor integrated circuitdevice as set forth in the above item 22, wherein the dielectric filmfor information storage substantially has a perovskite structure.

[0065] 24. The process for producing a semiconductor integrated circuitdevice, comprising:

[0066] (a) preparing a wafer for use in the production of asemiconductor integrated circuit device, wherein a part or the whole ofeach of a plurality of semiconductor elements is formed on the firstprincipal plane side of the wafer;

[0067] (b) leveling the first principal plane of the wafer having theplurality of semiconductor elements formed thereover by chemicalmechanical polishing;

[0068] (c) forming a conducting film, which constitutes a lowerelectrode of a capacitive element for information storage in a volatileor nonvolatile memory, over the leveled first principal plane of thewafer either directly or with a plurality of intermediate filmstherebetween;

[0069] (d) forming a high-dielectric or ferroelectric film, whichconstitutes a dielectric film of a capacitive element for informationstorage in a volatile or nonvolatile memory, over the first principalplane of the wafer having a layer of the lower electrode formedthereover either directly or with a plurality of intermediate filmstherebetween by sputtering using a target having a density of as high asat least 90% of the theoretical density at least in the portion thereofsubject to sputtering; and

[0070] (e) forming a conducting film, which constitutes an upperelectrode of a capacitive element for information storage in a volatileor nonvolatile memory, over the first principal plane of the waferhaving the dielectric film formed thereover either directly or with oneor more intermediate films therebetween.

[0071] 25. The process for producing a semiconductor integrated circuitdevice as set forth in the above item 24, wherein the dielectric filmfor information storage has a relative dielectric constant of at least20 in the final product.

[0072] 26. The process for producing a semiconductor integrated circuitdevice as set forth in the above item 25, wherein the dielectric filmfor information storage substantially has a perovskite structure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0073]FIG. 1 is a plan view of the essential part of a semiconductorsubstrate, which illustrates the process for producing a semiconductorintegrated circuit device according to an embodiment of the presentinvention;

[0074]FIG. 2 is a cross-sectional view of the essential part of asemiconductor substrate, which illustrates the process for producing asemiconductor integrated circuit device according to an embodiment ofthe present invention;

[0075]FIG. 3 is a cross-sectional view of the essential part of asemiconductor substrate, which illustrates the process for producing asemiconductor integrated circuit device according to an embodiment ofthe present invention;

[0076]FIG. 4 is a cross-sectional view of the essential part of asemiconductor substrate, which illustrates the process for producing asemiconductor integrated circuit device according to an embodiment ofthe present invention;

[0077]FIG. 5 is a cross-sectional view of the essential part of asemiconductor substrate, which illustrates the process for producing asemiconductor integrated circuit device according to an embodiment ofthe present invention;

[0078]FIG. 6 is a cross-sectional view of the essential part of asemiconductor substrate, which illustrates the process for producing asemiconductor integrated circuit device according to an embodiment ofthe present invention;

[0079]FIG. 7 is a cross-sectional view of the essential part of asemiconductor substrate, which illustrates the process for producing asemiconductor integrated circuit device according to an embodiment ofthe present invention;

[0080]FIG. 8 is a cross-sectional view of the essential part of asemiconductor substrate, which illustrates the process for producing asemiconductor integrated circuit device according to an embodiment ofthe present invention;

[0081]FIG. 9 is a cross-sectional view of the essential part of asemiconductor substrate, which illustrates the process for producing asemiconductor integrated circuit device according to an embodiment ofthe present invention;

[0082]FIG. 10 is a cross-sectional view of the essential part of asemiconductor substrate, which illustrates the process for producing asemiconductor integrated circuit device according to an embodiment ofthe present invention;

[0083]FIG. 11 is a cross-sectional view of the essential part of asemiconductor substrate, which illustrates the process for producing asemiconductor integrated circuit device according to an embodiment ofthe present invention;

[0084]FIG. 12 is a cross-sectional view of the essential part of asemiconductor substrate, which illustrates the process for producing asemiconductor integrated circuit device according to an embodiment ofthe present invention;

[0085]FIG. 13 is a cross-sectional view of the essential part of asemiconductor substrate, which illustrates the process for producing asemiconductor integrated circuit device according to an embodiment ofthe present invention;

[0086]FIG. 14 is a cross-sectional view of the essential part of asemiconductor substrate, which illustrates the process for producing asemiconductor integrated circuit device according to an embodiment ofthe present invention;

[0087]FIG. 15 is a cross-sectional view of the essential part of asemiconductor substrate, which illustrates the process for producing asemiconductor integrated circuit device according to an embodiment ofthe present invention;

[0088]FIG. 16 is a constitutional diagram of the essential part ofsputtering equipment for use in the process for producing asemiconductor integrated circuit device according to an embodiment ofthe present invention;

[0089]FIG. 17 is a model diagram showing the perovskite crystalstructure of PZT;

[0090]FIG. 18 is a graph showing the relationship between the density ofa target and the residual dielectric polarization of a PZT film;

[0091]FIG. 19 is a graph showing the hysteresis curves of PZT films;

[0092]FIG. 20 is a cross-sectional view of the essential part of asemiconductor substrate, which illustrates the process for producing asemiconductor integrated circuit device according to an embodiment ofthe present invention;

[0093]FIG. 21 is a cross-sectional view of the essential part of asemiconductor substrate, which illustrates the process for producing asemiconductor integrated circuit device according to an embodiment ofthe present invention;

[0094]FIG. 22 is a cross-sectional view of the essential part of asemiconductor substrate, which illustrates the process for producing asemiconductor integrated circuit device according to an embodiment ofthe present invention; and

[0095]FIG. 23 is a cross-sectional view of the essential part of asemiconductor substrate, which illustrates the process for producing asemiconductor integrated circuit device according to an embodiment ofthe present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0096] An embodiment of the present invention will now be described indetail with reference to the accompanying drawings. It is to be notedthat, in all the figures for the explanation of the embodiments, thesame symbols are attached to the parts having the same functions, thusomitting repeated explanation thereof.

[0097]FIG. 1 is a plan view of a layout of memory cells of a DRAM (or aferroelectric RAM) according to this embodiment. Each of the memorycells adopts a cell with two points of intersection (folded bitlineconstitution) and a COB (capacitor over bitline) structure wherein acapacitor is disposed over a bitline. A transistor (memory cellselection MISFET) of each memory cell is connected via a bitline BL toperipheral circuit. The bitline BL is connected to one of n-typesemiconductor regions 8 (source and drain regions) of the memory cellselection MISFET through a connecting hole 14. The operation of thememory cell selection MISFET is controlled by a wordline WL (gateelectrode 6). This wordline WL (gate electrode 6) is connected toperipheral circuits. A capacitor C disposed over the bitline BL isconnected to the other one of the n-type semiconductor regions 8 (sourceand drain regions) of the memory cell selection MISFET through aconnecting hole 13. The capacitor C is connected via a plate electrode26 to peripheral circuits.

[0098] A first feature of this planar layout is that one plate electrode26 is disposed per two wordlines WL. This layout can diminish thecapacity of the plate electrode 26 to facilitate the control of thepotential of the plate electrode 26 with peripheral circuits. The numberof the plate electrodes 26 may alternatively be such as to be either oneper wordline WL or one per three wordlines WL. As the number of theplate electrodes 26 is increased as against the number of the wordlinesWL, however, the level of integration can hardly be raised. On the otherhand, as the number of the plate electrodes 26 is decreased as againstthe number of the wordlines WL, the capacity of each plate electrode 26is so increased that the control thereof with peripheral circuitsbecomes difficult. The optimum number of the plate electrodes 26 isvaried depending on the use of the DRAM (ferroelectric RAM).

[0099] A second feature of this planar layout is that the plateelectrodes 26 are extended in the same direction as that of thewordlines WL (gate electrodes 6). This enables the control of thepotential of each plate electrode 26 with peripheral circuits to beeffected in synchronizing that potential with the potential of thewordline WL.

[0100] In the production of these memory cells, a semiconductorsubstrate 1 made of p-type single-crystal silicon is first prepared, anda field oxide film 2 is then formed on the surface of the substrate 1 bythe selective oxidation (LOCOS) method, followed by ion implantation ofa p-type dopant (B) into the semiconductor substrate 1 to form a p-typewell 3, as shown in FIG. 2 (cross-sectional view taken along the lineA-A′ of FIG. 1). Subsequently, a p-type dopant (B) is ion-implanted intothe p-type well 3 to form a p-type channel stopper layer 4, and a gateoxide film 5 is then formed on the surface of the active region of thep-type well 3 surrounded by the field oxide film 2 according to athermal oxidation method.

[0101] The gate electrodes 6 (wordlines WL) of the memory cell selectionMISFETs are then formed as shown in FIG. 3. The gate electrodes 6(wordlines WL) are formed, for example, according to a procedurecomprising depositing a polycrystalline silicon film over thesemiconductor substrate 1 by CVD, then depositing a TiN film and a Wfilm by sputtering, and further depositing a silicon nitride film 7 as acap insulating film by plasma CVD, and then patterning these films byetching using a photoresist as a mask. The polycrystalline silicon filmthat constitutes a part of each gate electrode 6 (wordline WL) is dopedwith an n-type dopant (P) to lower the resistance thereof.

[0102] As shown in FIG. 4, an n-type dopant (P) is then ion-implantedinto the p-type well 3 to form n-type semiconductor regions 8, 8 (sourceand drain regions) of the memory cell selection MISFETs in the p-typewell 3 on both sides of each gate electrode 6 (wordline WL).

[0103] As shown in FIG. 5, side wall spacers 9 are then formed on theside walls of the gate electrodes 6 (wordlines WL). The side wallspacers 9 are formed according to a procedure comprising depositing asilicon nitride film over the gate electrodes 6 (wordlines WL) by plasmaCVD and then processing the silicon nitride film by anisotropic etching.

[0104] As shown in FIG. 6, a silicon oxide film 10 and a BPSG(boron-doped phospho silicate glass) film 11 are then deposited over thememory cell selection MISFETs, and the BPSG film 11 is then polished bythe chemical mechanical polishing (CMP) method to level the surfacethereof.

[0105] As shown in FIG. 7, a polycrystalline silicon film 12 is thendeposited over the BPSG film 11 by CVD, followed by the etching of thepolycrystalline silicon film 12, the BPSG film 11, the silicon oxidefilm 10 and the gate oxide film 5 by using a photoresist as a mask,whereby a connecting hole 13 is formed over one (n-type semiconductorregion 8) of the source and drain regions of each memory cell selectionMISFET while forming a connecting hole 14 over the other one (n-typesemiconductor region 8). In this etching, the silicon nitride films 7formed over the gate electrodes 6 (wordlines WL) of the memory cellselection MISFETs and the silicon nitride side wall spacers 9 formed onthe side walls thereof are only slightly etched to enable the connectingholes 13 and 14 of a minute diameter to be formed by self alignment evenwithout providing a room for aligning the connecting holes 13, 14 withthe gate electrodes 6 (wordlines WL).

[0106] As shown in FIG. 8, polycrystalline silicon plugs 15 are thenembedded in the connecting holes 13, 14. These plugs 15 are formedaccording to a procedure comprising depositing a polycrystalline siliconfilm over polycrystalline silicon films 12 as mentioned above by CVD,and etching back this polycrystalline silicon film and thepolycrystalline silicon films 12 to remove them. The polycrystallinesilicon film that constitutes the plugs 15 is doped with an n-typedopant (P). The plugs 15 may alternatively be formed by embedding, forexample, TiN, W, Ti or Ta instead of the polycrystalline silicon.

[0107] As shown in FIG. 9, a silicon oxide film 16 is then depositedover the BPSG films 11 by CVD and then etched using a photoresist as amask to remove the silicon oxide film 16 overlying the connecting holes14. Thereafter, bitlines BL are formed over the connecting holes 14, asshown in FIG. 10. The bitlines BL are formed according to a procedurecomprising depositing a TiN film and a W film over the silicon oxidefilm 16 by sputtering, further depositing a silicon nitride film 17 as acap insulating film by plasma CVD, and then patterning these films byetching using a photoresist as a mask.

[0108] As shown in FIG. 11, side wall spacers 18 are then formed on theside walls of the bitlines BL. The side wall spacers 18 are formedaccording to a procedure comprising depositing a silicon nitride filmover the bitlines BL by plasma CVD and then processing it by anisotropicetching.

[0109] As shown in FIG. 12, a BPSG film 19 of about 300 nm in thicknessis then deposited by CVD and reflowed over the bitlines BL, and the BPSGfilm 19 and the silicon oxide films 16 are then etched using aphotoresist as a mask to form connecting holes 20 over the connectingholes 13 formed over the other ones (n-type semiconductor regions 8) ofthe source and drain regions of the memory cell selection MISFETs Qt. Inthis etching, the silicon nitride films 17 overlying the bitlines BL andthe side wall spacers 18 on the side walls thereof serve as etchingstoppers to enable the connecting holes 20 to be formed by selfalignment like the connecting holes 13, 14.

[0110] As shown in FIG. 13, plugs 21 are embedded in the connectingholes 20. The plugs 21 are formed according to a procedure comprisingdepositing a TiN film and a W film over the BPSG films 19, for example,by sputtering, and then etching back these films. The plugs 21 may beformed by embedding polycrystalline silicone, TiN, W, Ti, Ta, etc.

[0111] Capacitors are then formed over the plugs 21. In forming thecapacitors, a barrier metal 22 is first deposited over the BPSG films 19by sputtering or the like, and a Pt (platinum) film 23 a of about 175 nmin thickness is then deposited over the barrier metal 22. It is to benoted that the barrier metal 22, though not always necessary, iseffective in suppressing the diffusion of the lower electrode material(Pt) of the capacitors. TiN, Ti, etc. are usable as the material of thebarrier metal 22, the thickness of which may be about 20 nm.

[0112] As shown in FIG. 15, a PZT film 24 as one kind of ferroelectricfilm is then deposited over the Pt film 23 a.

[0113]FIG. 16 is a constitutional diagram of the essential part of thesputtering equipment for use in the deposition of the PZT film 24. Adiscoid packing plate 102 as a target holding means and a stage 104connected to an RF power source 103 are disposed facing each otherinside a chamber 101 as the treatment chamber of this sputteringequipment 100. A target 105 made of a hot-pressed PZT sinter is attachedto the lower surface of the packing plate 102. On the other hand, asemiconductor substrate (wafer) 1 is mounted on the upper surface of thestage 104.

[0114] A shield 107 for forming a high-density plasma 106 in a gapbetween the target 105 and the semiconductor substrate 1 is providednear the stage 104 inside the chamber 101. The wall of the chamber 101is provided with a gas inlet pipe 108 for feeding an inert gas such asAr into the chamber 101 and an exhaust pipe 109 for discharging the gasinside the chamber 101.

[0115] The conditions of formation of the PZT film 24 are, by way ofexample, such that the substrate temperature is room temperature, thepressure in the chamber is 5 to 10 mTorr, the Ar flow rate is 10 to 30sccm, the RF power is 1 kW, and the gap between the target and thesubstrate is 50 mm, while the thickness of the PZT film 24 thus formedis about 250 nm.

[0116]FIG. 17 is a model diagram showing the perovskite crystalstructure of PZT. As shown therein, a unit cell of this perovskitecrystal is in the form of an octagon wherein a Ti (or Zr) atom isdisposed at the center (B site) thereof, Pb atoms are respectivelydisposed at the eight vertices (A sites) thereof, and 0 (oxygen) atomsare respectively disposed at the centers of the eight faces thereof.Polarization occurs by the displacement of the Ti (Zr) disposed at the Bsite when a predetermined voltage is applied along the direction of thec axis, which is a polarization axis.

[0117] Thus, PZT is always liable to undergo an oxygen defect because ittakes a perovskite crystal structure including much O (oxygen). Further,the formed film has such a feature that PbO is liable to come off thecrystal when the film is treated at a high temperature (at least 850°C.).

[0118] The target 105 to be used in this embodiment has a density of atleast 90% of the theoretical density of the foregoing perovskitecrystal. Herein, the density of the target can be calculated in thefollowing manner:

[0119] Specifically, when Na is the Avogadro number, V is the volume ofa target, M is the weight of the target, D is the theoretical density ofa perovskite crystal (stoichiometric composition), and a, b and c arethe respective lengths of the crystallographic axes (a, b and c axes) ofthe perovskite crystal actually measured by X-ray diffractometry, thenthe weight of the unit cell, the theoretical density (D) of theperovskite crystal and the density of the target are represented by thefollowing respective formulae because the respective atomic weights andnumber of atoms, per unit cell, of Pb, 0, Ti and Zr as the constituentelements of PZT are such that Pb=207.2 and (⅛)×8=1 for Pb, O=16.00 and(½)×6=3 for O, Ti=47.90 and 1×1×X=X for Ti, and Zr=91.22 and1×1×(1−X)=1−X for Zr:

[0120] weight of unitcell={207.2×1+16.00×3+47.90×X+91.22×(1−X)}÷Na=Dx{abc},

[0121] theoretical density(D)={207.2×1+16.00×3+47.90×X+91.22×(1−X)}÷Na÷{abc}, and

[0122] density of target (%)={M÷V}÷D×100.

[0123] On the other hand, in the case of a crystal structure having acomposition departing from the stoichiometric ratio, i.e., anonstoichiometric composition, such as Pb_(1.1)Zr_(0.5)Ti_(0.5)O_(3.1),the theoretical density is estimated in terms of the density of astoichiometric composition (PbZr_(0.5)Ti_(0.5)O₃) plus that of aconstituent [(PbO)_(0.1)] departing from the stoichiometric ratio.

[0124]FIG. 18 is a graph showing the relationship between the density ofa target and the residual dielectric polarization of a PZT film, whileFIG. 19 is a graph showing the hysteresis curves of PZT films.

[0125] As shown in FIG. 18, the PZT films formed using high-densitytargets each having a density of at least 90% are increased in the valueof the residual dielectric polarization (2Pr) as compared with the PZTfilms formed using low-density targets each having a density lower than90%, thus being improved in electrical property. On the other hand, asshown in FIG. 19, the PZT film formed using a high-density target isimproved in hysteresis characteristics as compared with the PZT filmformed using a low-density target, whereby a high value of residualdielectric polarization (2Pr) can be obtained even at a low potential.This is because the use of a high-density target having a density closeto the theoretical density (D) of a perovskite crystal enables clusters(fine crystals) close to the perovskite crystal to be formed duringsputtering, whereby the structure thereof can be maintained even afterfilm formation.

[0126] More specifically, a crystalline target like a PZT target is anaggregate (polycrystalline material) of crystals in itself and issputtered usually in the form of a cluster of a number of targetconstituents (unit cells) during sputtering, which deposits as a lumpover a substrate. Accordingly, whether the crystallinity of the clusteritself is good or not determines whether the dielectric properties ofthe film in the process of its formation or as a final product are goodor not.

[0127] Meanwhile, since the shapes of innumerable grains in a film aredetermined once the film is annealed after the formation thereof,subsequent annealing in oxygen, even if additionally effected, cannot beexpected to secure further crystallization of grains although it maycontribute to crystallographic recovery in the grains. In other words,the crystallizability of grains during first annealing after the filmformation is important.

[0128] Although a description has been made of the case where a PZTtarget is used, the use of a high-density target having a densityexceeding 90% of the theoretical density of a crystal enables a thinfilm improved in dielectric constant, residual dielectric polarization,hysteresis characteristics, etc. to be obtained even in the case wherethe capacitive insulating film of a capacitor is formed using a targetmade of a high-dielectric material such as Ta₂O₅ or BST, or a variety offerroelectric material such as PLT (PbLa_(x)Ti_(1-X)O₃), PLZT(PbLa_(Y)Zr_(x)Ti_(1-X)O₃), SBT (Sr_(x)Bi_(Y)TaO), PbTiO₃, SrTiO₃ orBaTiO₃.

[0129] Targets produced by the molecular beam epitaxial growth methodcapable of facilitating the formation of high-quality crystals besidesthe ordinary hot-pressing (sintering under high-temperaturehigh-pressure sintering) method are suitable as the target to be used inthis embodiment of the present invention. It is also possible to applythe plasma sintering method, the explosive sintering method, the laserablation method, etc.

[0130] Subsequently, the aforementioned PZT film 24 is annealed in anoxygen atmosphere at 500 to 800° C. to grow fine clusters into crystalgrains. Thereafter, a Pt film 25 a of about 100 nm in thickness isdeposited over the PZT film 24, as shown in FIG. 20. Subsequently, thePt film 25 a, the PZT film 24, the Pt film 23 a and the barrier metal 22are dry-etched using a photoresist formed over the Pt film 25 a as amask to form capacitors C each comprising a barrier metal 22, a lowerelectrode 23, a PZT film 24 and an upper electrode 25 as shown in FIG.21.

[0131] Also it is possible to use Ir, IrO₂, Rh, RhO₂, Os, OsO_(z), Ru,RuO₂, Re, ReO₃, Pd, Au or a laminated film thereof, in addition to Pt,as the material of the lower electrodes 23 and the upper electrodes 25.In the case of RuO₂, IrO₂, etc., a thin film having a good coverage canbe formed through the deposition thereof by MOCVD. Further, thedeposition of Ru, Ir or the like, each having high barrier propertiesagainst oxygen, over the above-mentioned thin film can improve theoxidation resistance of the film. If the oxidation in the interfaces ofthe capacitive insulating films can be suppressed, W, Al, TiN, Ta, Cu,Ag, or a laminated film or the like thereof may alternatively be used asthe upper electrode material.

[0132] The photoresist 27 over each capacitor C is then removed byashing. As shown in FIG. 22, a reflowable insulating film 28 such as aBPSG film is then deposited for the protection of the capacitors C, andthe surface thereof is then leveled by chemical mechanical polishing(CMP) to expose the surface of each upper electrode 25. In this case,although complete leveling is not indispensable, it is desired that theinsulating film 28 be leveled as much as possible in order to enhancethe reliability of wirings to be formed over the insulating film 28 in alater step. In order to enhance the effect of protecting the capacitorsC, the insulating film 28 may be deposited after the deposition of athin film made of an oxide of Ti, Sr, Ba or the like, each having a goodaffinity for the constituent material of the capacitors C. A CVD siliconoxide film formed using an organosilicon compound gas may alternativelybe used instead of the reflowable insulating film 28. An organicinsulating material such as a polyimide resin may also alternatively beused. The insulating film may be leveled by etching back instead of CMP,and may be dispensed with particularly in the case where a difference inlevel due to the capacitors is small.

[0133] As shown in FIG. 23, plate electrodes 26 each common to aplurality of memory cells are then formed over the insulating film 28.Various conducting materials used in the conventional silicon LSIprocesses, such as a polycrystalline silicon film, a W film, etc., canbe used as the material of the plate electrodes. When the underlyinglayer has been sufficiently leveled, use is made of a conductingmaterial capable of forming a film by sputtering. On the other hand,when the underlying layer has a difference in level, use is made of aconducting material capable of forming a film by CVD.

[0134] According to the foregoing procedure, the formation of memorycells of a DRAM (ferroelectric RAM) in this embodiment is substantiallycompleted. In the case of an actual DRAM (ferroelectric RAM), it goeswithout saying that about two layers of wirings must further be formedover the plate electrodes 26 to connect the memory cells to peripheralcircuits, and that the whole body of the semiconductor substrate 1 mustbe sealed with a resin package or the like.

[0135] Although the invention made by the present inventors has beenspecifically described based on the embodiment, the present inventionis, needless to say, capable of various modifications within the scopeof the invention without being limited to the foregoing embodiment.

[0136] Although the foregoing embodiment has been described inconnection with the case where high-dielectric or ferroelectric thinfilms are formed as the capacitive insulating films of the capacitors ofa DRAM (ferroelectric RAM), the process of the invention can be appliedto the production of an MFSFET, an MFSMISFET, etc. wherein ferroelectricthin films are formed as gate insulating films.

[0137] Now the effects secured by the representative embodiments of theinvention disclosed in the instant application will be briefed.

[0138] (1) According to the present invention wherein a target having adensity of at least 90% of the theoretical value is used in forming ahigh-dielectric thin film or a ferroelectric thin film over a substrateby sputtering, it is possible to obtain a high-dielectric orferroelectric thin film improved in dielectric constant, residualdielectric polarization and hysteresis characteristics.

[0139] (2) Since the effect described in the item (1) above serves toincrease the amount of electric charge storable in each capacitor of aDRAM, the miniaturization and integration of a DRAM can be promoted.

[0140] (3) Since the effect described in the item (1) above serves toimprove the resistance to the fatigues of capacitive insulating filmsthrough repetition of polarization inversion and suppress a decrease inresidual dielectric polarization, the possible number of times of datarewriting in a ferroelectric RAM can be increased. Further, since suchan improvement in the fatigue resistance of the capacitive insulatingfilms facilitates the conversion of the 2-transistor/2-capacitorstructure of a memory cell of a ferroelectric RAM to a1-transistor/1-capacitor structure, the miniaturization and integrationof a ferroelectric RAM can be promoted.

[0141] (4) Since the effect described in the item (1) above serves todecrease the number of times, temperature, and time of annealingeffected in an oxygen atmosphere for the recovery of the properties of ahigh-dielectric or ferroelectric thin film, the deterioration of theproperties of the film attributed to annealing can be so suppressed asto improve the reliability and production yield of DRAMs andferroelectric RAMs.

What is claimed is:
 1. A process for producing a semiconductorintegrated circuit device, comprising the steps of: (a) emittingsputtered particles by colliding inert gas ions under a vacuum conditionwith a first surface of a high-dielectric or ferroelectric sputteringtarget having a first chemical composition and having a density of saidfirst chemical composition which is not less than 90% of a theoreticaldensity thereof; (b) forming a high-dielectric or ferroelectric film bydepositing the sputtered particles under the vacuum condition over alower electrode overlying a first major surface of a semiconductorwafer, said high-dielectric or ferroelectric film having a secondchemical composition substantially the same as the first chemicalcomposition; and (c) after step (b), improving crystallinecharacteristics of the high-electric or ferroelectric film by performingan annealing treatment thereto in a gas ambient including an oxygen gas.2. A process for producing a semiconductor integrated circuit deviceaccording to claim 1, wherein the high-dielectric or ferroelectric filmand the lower electrode constitute a memory capacitor of a memory cell.3. A process for producing a semiconductor integrated circuit deviceaccording to claim 2, wherein the first chemical composition, of thetarget, is shifted from a stoichiometric composition.
 4. A process forproducing a semiconductor integrated circuit device according to claim3, further comprising the step of: (d) prior to step (a), planarizingthe first major surface of the semiconductor wafer by a treatmentincluding chemical mechanical polishing.
 5. A process for producing asemiconductor integrated circuit device, comprising the steps of: (a)emitting sputtered particles by colliding inert gas ions under a vacuumcondition with a first surface of a highdielectric or ferroelectricsputtering target, which is made of a double oxide and has a density notless than 90% of its theoretical density; and (b) forming ahigh-dielectric or ferroelectric film by depositing the sputteredparticles under the vacuum condition over a lower electrode overlying afirst major surface of a semiconductor wafer.
 6. A process for producinga semiconductor integrated circuit device, comprising the steps of: (a)emitting sputtered particles by colliding inert gas ions under a vacuumcondition with a first surface of a highdielectric or ferroelectricsputtering target having a density not less than 90% of its theoreticaldensity, a relative dielectric constant of said target being not lessthan 100; and (b) forming a high-dielectric or ferroelectric film bydepositing the sputtered particles under the vacuum condition over alower electrode overlying a first major surface of a semiconductorwafer.
 7. A process for producing a semiconductor integrated circuitdevice according to claim 6, wherein the high-dielectric orferroelectric film is made of BST, PZT, PLT, PLZT, SBT, PbTiO₃, SrTiO₃,or BaTiO₃.
 8. A process for producing a semiconductor integrated circuitdevice, comprising the steps of: (a) emitting sputtered particles bycolliding inert gas ions under a vacuum condition with a first surfaceof a high-dielectric or ferroelectric sputtering target having a densitynot less than 90% of its theoretical density, the crystalline structureof said target including a perovskite structure; and (b) forming ahigh-dielectric or ferroelectric film by depositing the sputteredparticles under the vacuum condition over a lower electrode overlying afirst major surface of a semiconductor wafer.
 9. A process for producinga semiconductor integrated circuit device according to claim 8, whereinthe high-dielectric or ferroelectric film is made of BST, PZT, PLT,PLZT, SBT, PbTiO₃, SrTiO₃, or BaTiO₃.
 10. A process for producing asemiconductor integrated circuit device, comprising the steps of: (a)emitting sputtered particles by colliding inert gas ions under a vacuumcondition with a first surface of a high-dielectric or ferroelectricsputtering target having a density not less than 90% of its theoreticaldensity; and (b) forming a high-dielectric or ferroelectric film bydepositing the sputtered particles under the vacuum condition over alower electrode overlying a first major surface of a semiconductorwafer.
 11. A process for producing a semiconductor integrated circuitdevice according to claim 10, wherein the ferroelectric film and thelower electrode constitute a memory capacitor of a nonvolatile memorycell.
 12. A process for producing a semiconductor integrated circuitdevice, comprising the steps of: (a) emitting sputtered particles bycolliding inert gas ions under a vacuum condition with a first surfaceof a highdielectric or ferroelectric sputtering target having a densitynot less than 90% of its theoretical density, a crystalline structure ofsaid target being a perovskite structure including Pb; and (b) forming ahigh-dielectric or ferroelectric film by depositing the sputteredparticles under the vacuum condition over a lower electrode overlying afirst major surface of a semiconductor wafer.
 13. A process forproducing a semiconductor integrated circuit device according to claim12, wherein the high-dielectric or ferroelectric film and the lowerelectrode constitute a memory capacitor of a nonvolatile memory cell.14. A process for producing a semiconductor integrated circuit device,comprising the steps of: (a) emitting sputtered particles by collidinginert gas ions under a vacuum condition with a first surface of ahigh-dielectric or ferroelectric sputtering target having a firstchemical composition and having a density of said first chemicalcomposition which is not less than 90% of its theoretical densitythereof, at the portion of the first surface of the target to besputtered; and (b) forming a high-dielectric or ferroelectric film bydepositing the sputtered particles under the vacuum condition over alower electrode overlying a first major surface of a semiconductorwafer, said high-dielectric or ferroelectric film having a secondchemical composition substantially the same as the first chemicalcomposition.
 15. A process for producing a semiconductor integratedcircuit device, comprising the steps of: (a) emitting sputteredparticles by colliding inert gas ions under a vacuum condition with afirst surface of a high-dielectric or ferroelectric sputtering target,which is made of a double oxide and has a density not less than 90% ofits theoretical density at a portion of the first surface of the targetto be sputtered, and (b) forming a high-dielectric or ferroelectric filmby depositing the sputtered particles under the vacuum condition over alower electrode overlying a first major surface of a semiconductorwafer.
 16. A process for producing a semiconductor integrated circuitdevice according to claim 15, further comprising the steps of: (c) afterstep (b), improving crystalline characteristics of the high-dielectricor ferroelectric film by performing an annealing treatment thereto in agas ambient including an oxygen gas.
 17. A process for producing asemiconductor integrated circuit device according to claim 16, furthercomprising the step of: (d) prior to step (a), planarizing the firstmajor surface of the semiconductor wafer by a treatment includingchemical mechanical polishing.
 18. A process for producing asemiconductor integrated circuit device according to claim 17, whereinthe high-dielectric or ferroelectric film and the lower electrodeconstitute a memory capacitor of a memory cell.
 19. A process forproducing a semiconductor integrated circuit device according to claim18, wherein the lower electrode includes at least one material selectedfrom the group consisting of platinum, ruthenium, and iridium, andoxides thereof.
 20. A process for producing a semiconductor integratedcircuit device according to claim 18, wherein the lower electrodeincludes at least one material selected from the group consisting ofplatinum, ruthenium, rhodium, osmium, rhenium, palladium, gold andiridium, and oxides thereof.
 21. A process for producing a semiconductorintegrated circuit device, comprising the steps of: (a) emittingsputtered particles by colliding inert gas ions under a vacuum conditionwith a first surface of a high-dielectric or ferroelectric sputteringtarget having a density not less than 90% of its theoretical density ata portion of the first surface of the target to be sputtered, a relativedielectric constant of said target being not less than 100; and (b)forming a high-dielectric or ferroelectric film by depositing thesputtered particles under the vacuum condition over a lower electrodeoverlying a first major surface of a semiconductor wafer.
 22. A processfor producing a semiconductor integrated circuit device, comprising thesteps of: (a) emitting sputtered particles by colliding inert gas ionsunder a vacuum condition with a first surface of a highdielectric orferroelectric sputtering target having a density not less than 90% ofits theoretical density at a portion of the first surface of the targetto be sputtered, a crystalline structure of said target including aperovskite structure; and (b) forming a high-dielectric or ferroelectricfilm by depositing the sputtered particles under the vacuum conditionover a lower electrode overlying a first major surface of asemiconductor wafer.
 23. A process for producing a semiconductorintegrated circuit device, comprising the steps of: (a) emittingsputtered particles by colliding inert gas ions under a vacuum conditionwith a first surface of a high-dielectric or ferroelectric sputteringtarget having a density not less than 90% of its theoretical density ata portion of the first surface of the target to be sputtered; and (b)forming a high-dielectric or ferroelectric film by depositing thesputtered particles under the vacuum condition over a lower electrodeoverlying a first major surface of a semiconductor wafer.
 24. A processfor producing a semiconductor integrated circuit device, comprising thesteps of: (a) emitting sputtered particles by colliding inert gas ionsunder a vacuum condition with a first surface of a high-dielectric orferroelectric sputtering target having a density not less than 90% ofits theoretical density at a portion of the first surface of the targetto be sputtered, a crystalline structure of said target being aperovskite structure including Pb; and (b) forming a high-dielectric orferroelectric film by depositing the sputtered particles under thevacuum condition over a lower electrode overlying a first major surfaceof a semiconductor wafer.